The von Neumann architecture is the foundation of modern computers. Under this architecture, programs and data are stored together, instructions and data need to be accessed from the same storage space, and transmitted through the same bus, and cannot be executed simultaneously. According to the von Neumann system, the operation of the CPU is divided into the following 5 stages: instruction fetching stage, instruction decoding stage, instruction execution stage, memory access stage and result write-back stage. [1]
Fetch instruction (IF), which is the process of retrieving an instruction from the main memory and placing it in the instruction register. The value in the program counter indicates the location of the current instruction in the main memory. After an instruction is fetched, the value in the program counter (PC) will automatically increase according to the length of the instruction word. [1]
Instruction Decoding Stage (ID, instruction decode): After the instruction is retrieved, the instruction decoder splits and interprets the retrieved instruction according to the predetermined instruction format, identifying and distinguishing different instruction categories as well as various methods for obtaining operands. Modern CISC processors will further enhance the splitting to improve parallelism and efficiency. [1]
Execution stage (EX, execute): This stage implements the functionality of the instruction. Different parts of the CPU are connected to perform the required operations.
Memory access stage (MEM, memory): According to the instruction requirements, it accesses the main memory and reads the operand. The CPU obtains the address of the operand in the main memory and reads the operand from the main memory for the operation. Some instructions do not need to access the main memory, so this stage can be skipped. [1]
The Result Write Back stage (WB, write back) is the final stage. In this stage, the run result data from the Execution Instruction stage is “written back” to a certain storage form. The result data is generally written into the internal registers of the CPU, so that it can be quickly accessed by subsequent instructions; many instructions also change the status of the Program Status Word register, where the flags indicate different operation results and can be used to influence the program’s actions. [1]
After the instruction execution is completed and the result data is written back, if no unexpected events (such as result overflow, etc.) occur, the computer will obtain the address of the next instruction from the program counter and start a new cycle. The next instruction cycle will sequentially fetch the next instruction. [1] Many complex CPUs can extract multiple instructions at once, decode them, and execute them simultaneously.